R5F104FCAFP datasheet(84/207 Pages) RENESAS

部件名	R5F104FCAFP

功能描述	True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

PDF	207 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

84 / 207 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0131EJ0350 Rev.3.50

84 of 200

Jun 30, 2020

(5) During communication at same potential (simplified I2C mode) (1/2)

(TA = –40 to +85°C, 1.6 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCLr clock frequency

fSCL

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

1000

Note 1

400

Note 1

400

Note 1

kHz

1.8 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

400

Note 1

400

Note 1

400

Note 1

kHz

1.8 V

≤ EVDD0 < 2.7 V,

Cb = 100 pF, Rb = 5 k

300

Note 1

300

Note 1

300

Note 1

kHz

1.7 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

250

Note 1

250

Note 1

250

Note 1

kHz

1.6 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

–

250

Note 1

250

Note 1

kHz

Hold time when SCLr = “L”

tLOW

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

475

1150

1.8 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

1.8 V

≤ EVDD0 < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550

1.7 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

1850

1.6 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

–

1850

Hold time when SCLr = “H”

tHIGH

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

475

1150

1.8 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

1.8 V

≤ EVDD0 < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550

1.7 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

1850

1.6 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

–

1850

(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)

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