R5F104FCAFP datasheet(99/207 Pages) RENESAS

99 / 207 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0131EJ0350 Rev.3.50

99 of 200

Jun 30, 2020

(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)

(TA = –40 to +85°C, 1.8 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp high-/low-level

width

tKH2,

tKL2

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

tKCY2/2 –

tKCY2/2

– 50

tKCY2/2

– 50

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

tKCY2/2 –

tKCY2/2

– 50

tKCY2/2

– 50

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2

tKCY2/2 –

tKCY2/2

– 50

tKCY2/2

– 50

SIp setup time

(to SCKp

↑) Note 3

tSIK2

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

1/fMCK

+ 20

1/fMCK

+ 30

1/fMCK

+ 30

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

1/fMCK

+ 20

1/fMCK

+ 30

1/fMCK

+ 30

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2

1/fMCK

+ 30

1/fMCK

+ 30

1/fMCK

+ 30

SIp hold time

(from SCKp

↑) Note 4

tKSI2

1/fMCK +

1/fMCK

+ 31

1/fMCK

+ 31

Delay time from

SCKp

↓ to SOp output

Note 5

tKSO2

4.0 V

≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2/fMCK

+ 120

2/fMCK

+ 573

2/fMCK

+ 573

2.7 V

≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2/fMCK

+ 214

2/fMCK +

573

2/fMCK +

573

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

2/fMCK

+ 573

2/fMCK +

573

2/fMCK +

573

Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps

2. Use it with EVDD0

≥ Vb.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 20- to

52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SOp pin and SCKp pin

by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see

the DC characteristics with TTL input buffer selected.

(Remarks are listed on the next page.)

R5F104FCAFP 数据表(PDF) 99 Page - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 99 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

R5F104FCAFP 数据表(PDF) 99 Page - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 99 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载