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R5F104FCAFP 数据表(PDF) 85 Page - Renesas Technology Corp |
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R5F104FCAFP 数据表(HTML) 85 Page - Renesas Technology Corp |
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85 / 207 page  RL78/G13 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 85 of 200 Jun 30, 2020 (5) During communication at same potential (simplified I2C mode) (2/2) (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 k Ω 1/fMCK + 85 Note2 1/fMCK + 145 Note2 1/fMCK + 145 Note2 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 k Ω 1/fMCK + 145 Note2 1/fMCK + 145 Note2 1/fMCK + 145 Note2 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k Ω 1/fMCK + 230 Note2 1/fMCK + 230 Note2 1/fMCK + 230 Note2 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Ω 1/fMCK + 290 Note2 1/fMCK + 290 Note2 1/fMCK + 290 Note2 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Ω – 1/fMCK + 290 Note2 1/fMCK + 290 Note2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 k Ω 0 305 0 305 0 305 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 k Ω 0 355 0 355 0 355 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k Ω 0 405 0 405 0 405 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Ω 0 405 0 405 0 405 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Ω – 0 405 0 405 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) |
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