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R5F104FCAFP 数据表(PDF) 114 Page - Renesas Technology Corp

部件名 R5F104FCAFP
功能描述  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 114 Page - Renesas Technology Corp

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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
R01DS0131EJ0350 Rev.3.50
114 of 200
Jun 30, 2020
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = –40 to +85°C, 2.4 V
≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
1.05
V
Internal reference voltage
VBGR
Setting ADS register = 81H
1.38
1.45
1.5
V
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
temperature
–3.6
mV/°C
Operation stabilization wait time
tAMP
5
µs
2.6.3 POR circuit characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Detection voltage
VPOR
The power supply voltage is rising.
1.47
1.51
1.55
V
VPDR
The power supply voltage is falling.
1.46
1.50
1.54
V
Minimum pulse widthNote
TPW
300
µs
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
TPW
VPOR
VPDR or 0.7 V
Supply voltage (VDD)



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