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R5F104FCAFP 数据表(PDF) 203 Page - Renesas Technology Corp

部件名 R5F104FCAFP
功能描述  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 203 Page - Renesas Technology Corp

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C - 3
Rev.
Date
Description
Page
Summary
3.00
Aug 02, 2013
118
Modification of table in 2.6.2 Temperature sensor/internal reference voltage
characteristics
118
Modification of table and note in 2.6.3 POR circuit characteristics
119
Modification of table in 2.6.4 LVD circuit characteristics
120
Modification of table of LVD Detection Voltage of Interrupt & Reset Mode
120
Renamed to 2.6.5 Power supply voltage rising slope characteristics
122
Modification of table, figure, and remark in 2.10 Timing Specs for Switching
Flash Memory Programming Modes
123
Modification of caution 1 and description
124
Modification of table and remark 3 in Absolute Maximum Ratings (TA = 25°C)
126
Modification of table, note, caution, and remark in 3.2.1 X1, XT1 oscillator
characteristics
126
Modification of table in 3.2.2 On-chip oscillator characteristics
127
Modification of note 3 in 3.3.1 Pin characteristics (1/5)
128
Modification of note 3 in 3.3.1 Pin characteristics (2/5)
133
Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin
products (1/2)
135
Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin
products (2/2)
137
Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100-pin
products (1/2)
139
Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to 100-
pin products (2/2)
140
Modification of (3) Peripheral Functions (Common to all products)
142
Modification of table in 3.4 AC Characteristics
143
Addition of Minimum Instruction Execution Time during Main System Clock
Operation
143
Modification of figure of AC Timing Test Points
143
Modification of figure of External System Clock Timing
145
Modification of figure of AC Timing Test Points
145
Modification of description, note 1, and caution in (1) During communication at
same potential (UART mode)
146
Modification of description in (2) During communication at same potential
(CSI mode)
147
Modification of description in (3) During communication at same potential
(CSI mode)
149
Modification of table, note 1, and caution in (4) During communication at same
potential (simplified I2C mode)
151
Modification of table, note 1, and caution in (5) Communication at different
potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
152 to 154 Modification of table, notes 2 to 6, caution, and remarks 1 to 4 in (5)
Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
155
Modification of table in (6) Communication at different potential (1.8 V, 2.5 V,
3 V) (CSI mode) (1/3)
156
Modification of table and caution in (6) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)
157, 158
Modification of table, caution, and remarks 3 and 4 in (6) Communication at
different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3)
160, 161
Modification of table and caution in (7) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode)



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