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ES9842PRO 数据表(PDF) 40 Page - ESS Technology,Inc

部件名 ES9842PRO
功能描述  32-bit High-Performance 4-Channel ADC
PDF  167 Pages
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制造商  ESS [ESS Technology,Inc]
网页  http://www.esstech.com
标志 ESS - ESS Technology,Inc

ES9842PRO 数据表(HTML) 40 Page - ESS Technology,Inc

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CONFIDENTIAL ADVANCE INFORMATION
ES9842 PRO Product Datasheet
40
VERSION 0.5
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
TDM Slave Clock Rate Configurations
All configurations are 32-bit.
When using left justified mode (Register 10) remember to enable Register 33 – sync positive edge of frame to correct for
phase differences.
MCLK Frequency WS [kHz]
BCK
[MHz]
TDM
Mode
Channels
Register 2
[4:0] SELECT_ADC_NUM
Value
Divider
22.579 MHz
44.1
5.645
TDM 128
4
5’d3
4
88.2
11.290
4
5’d1
2
176.4
22.579
4
5’d0
1
44.1
11.290
TDM 256
8
5’d3
4
88.2
22.579
8
5’d1
2
44.1
22.579 TDM 512
16
5’d3
4
24.576 MHz
48
6.144
TDM 128
4
5’d3
4
96
12.288
4
5’d1
2
192
24.576
4
5’d0
1
48
12.288
TDM 256
8
5’d3
4
96
24.576
8
5’d1
2
48
24.576 TDM 512
16
5’d3
4
45.158 MHz
44.1
5.645
TDM 128
4
5’d7
8
88.2
11.290
4
5’d3
4
176.4
22.579
4
5’d1
2
44.1
11.290
TDM 256
8
5’d7
8
88.2
22.579
8
5’d3
4
44.1
22.579 TDM 512
16
5’d7
8
49.152 MHz
48
6.144
TDM 128
4
5’d7
8
96
12.288
4
5’d3
4
192
24.576
4
5’d1
2
48
12.288
TDM 256
8
5’d7
8
96
24.576
8
5’d3
4
48
24.576 TDM 512
16
5’d7
8
Table 11 - TDM Slave Clock Rate Configurations



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