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ES9842PRO 数据表(PDF) 48 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 48 Page - ESS Technology,Inc |
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48 / 167 page  CONFIDENTIAL ADVANCE INFORMATION ES9842 PRO Product Datasheet 48 VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM Switching Characteristics Test Conditions (unless otherwise noted) TA = 25oC, AVCC = AVCCL = AVCCR = +4.5V, AVDD = +3.3V, fs = 48kHz, MCLK = 49.152MHz, I2S output PARAMETER SYMBOL MINIMUM TYPICAL MAXIMUM UNIT MCLK timing Frequency fMCLK 20 - 50 MHz Analog ADC fADC 20 - 25 MHz Duty Cycle - 45 50 55 % Bit Clock Frequency PCM (LJ/I2S) Mode fbCLK - 2 x fs x TDM_LENGTH MCLK/2 MHz PCM (LJ/I2S) + Enable_64FS Mode fbCLK - - MCLK MHz TDM4 (4ch data line) fbCLK - 4 x fs x TDM_LENGTH MCLK MHz TDM8 (8ch data line) fbCLK - 8 x fs x TDM_LENGTH MCLK MHz TDM16 (16ch data line) fbCLK - 16 x fs x TDM_LENGTH MCLK MHz Frame Clock Normal Frequency PCM (LJ/I2S) Mode WS MCLK/4096 - MCLK/128 kHz PCM (LJ/I2S) + Enable_64FS Mode WS - - MCLK/64 kHz TDM4 (4ch data line) WS MCLK/4096 - MCLK/128 kHz TDM8 (8ch data line) WS MCLK/4096 - MCLK/256 kHz TDM16 (16ch data line) WS MCLK/4096 - MCLK/512 kHz Table 22 - Switching Characteristics Note: Analog ADC (fADC) on the clock distribution diagram must be between 20-25MHz. MCLK used must be divided by 1 or 2 to create fADC. |
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