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ES9842PRO 数据表(PDF) 95 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 95 Page - ESS Technology,Inc |
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95 / 167 page  VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM ES9842 PRO Product Datasheet 95 Delay Line Registers Register 60-59: I2S DECODER CONFIG Bits [15:14] [13:12] [11] [10] [9:0] Default 2'd0 2'd0 1'b0 1'b0 10'd0 Bits Mnemonic Description [15:14] I2S_DECODER_WORD_WIDTH Sets the number of bits in a channel. • 2'd0: 32 bits (default) • 2'd1: 24 bits • 2'd2: 16 bits • 2'd3: Reserved [13:12] I2S_DECODER_BIT_DEPTH Sets the number of bits of data. • 2'd0: 32 bits (default) • 2'd1: 24 bits • 2'd2: 16 bits • 2'd3: Reserved [11] I2S_DECODER_POSEDGE_FRAME Sets where the frame starts. • 1'b0: Indicates frame starts on negedge of WS (default) • 1'b1: Indicates frame starts on posedge of WS [10] ENABLE_I2S_DECODER Enables I2S decoder. • 1'b0: Disabled (default) • 1'b1: Enabled [9:0] I2S_DECODER_BIT_START Indicates the MSB-2 position of the data from the frame start. Valid from 10'h000 to 10'h3FF Register 62-61: DELAY LINE CONFIG Bits [15:10] [9] [8:0] Default 6'd10 1'b0 9'd0 Bits Mnemonic Description [15:10] RESERVED NA [9] ENABLE_CLK_DL Enables delay line clock and data output. • 1'b0: Disabled (default) • 1'b1: Enabled [8:0] PROG_DELAY_LINE Sets the length of the delay line. |
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