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ES9842PRO 数据表(PDF) 87 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 87 Page - ESS Technology,Inc |
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87 / 167 page  VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM ES9842 PRO Product Datasheet 87 Register 34: SYNC CONTROL Bits [7] [6] [5] [4] [3] [2] [1] [0] Default 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b1 Bits Mnemonic Description [7] AUTO_ADC_CLKDIV_SYNC When enabled, the analog ADC clock divider is only allowed to change synchronously to the reference. • 1'b0: Auto sync disabled (default) • 1'b1: Auto sync enabled [6] AUTO_CLK_IADC_PHASE_SYNC Allows phase of CLK_IADC to be tuned automatically according to ADC input data. Only used when SYS_CLK is faster than CLK_IADC. • 1'b0: CLK_IADC phase tuning disabled (default) • 1'b1: Auto CLK_IADC phase tuning [5] AUTO_DSD_PHASE_SYNC Uses DSD clock input from GPIO1 as the sync reference, unless DSD_SYNC_TO_1FS is set. • 1'b0: DSD clock is not the sync reference (default) • 1'b1: DSD clock is the sync reference, unless DSD_SYNC_TO_1FS is set [4] AUTO_WS_PHASE_SYNC Uses WS input from GPIO2 as the sync reference, if AUTO_DSD_PHASE_SYNC is not set. • 1'b0: WS is not the sync reference • 1'b1: WS is the sync reference, if AUTO_DSD_PHASE_SYNC is not set (default) [3] AUTO_ICG_EN_SYNC When enabled, the clock dividers and ADC enables are only allowed to change synchronously to the reference. • 1'b0: Auto sync disabled • 1'b1: Auto sync enabled (default) [2] AUTO_ICG_SYNC Allows programmable clock dividers to auto sync to the reference. • 1'b0: Auto sync disabled • 1'b1: Auto sync enabled (default) [1] AUTO_FIR_SYNC Allows FIR to auto sync to the reference. • 1'b0: Auto sync disabled • 1'b1: Auto sync enabled (default) [0] AUTO_FS_SYNC Allows FS signals to auto sync to the reference. • 1'b0: Auto sync disabled • 1'b1: Auto sync enabled (default) |
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