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ES9842PRO 数据表(PDF) 70 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 70 Page - ESS Technology,Inc |
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70 / 167 page  CONFIDENTIAL ADVANCE INFORMATION ES9842 PRO Product Datasheet 70 VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM Register 6: DSD CONFIG Bits [7:6] [5] [4] [3] [2] [1] [0] Default 2'b00 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 Bits Mnemonic Description [7:6] RESERVED NA [5] DSD_DDR Enables DSD double-data-rate (DDR) output. In the DDR mode, DSD data is valid on both pos/neg edges of DSD clock. Otherwise, DSD data is valid only on positive edge of DSD clock. [4] DSD_MASTER_MODE Enables DSD master mode and generates DSD clock. • 1'b0: Disabled (default) • 1'b1: Enabled [3] ENABLE_DSD_CLK_CH4 Enables Ch4 DSD encoding clock. • 1'b0: DSD clock disabled (default) • 1'b1: DSD clock enabled [2] ENABLE_DSD_CLK_CH3 Enables Ch3 DSD encoding clock. • 1'b0: DSD clock disabled (default) • 1'b1: DSD clock enabled [1] ENABLE_DSD_CLK_CH2 Enables Ch2 DSD encoding clock. • 1'b0: DSD clock disabled (default) • 1'b1: DSD clock enabled [0] ENABLE_DSD_CLK_CH1 Enables Ch1 DSD encoding clock. • 1'b0: DSD clock disabled (default) • 1'b1: DSD clock enabled |
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