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ES9842PRO 数据表(PDF) 73 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 73 Page - ESS Technology,Inc |
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73 / 167 page  VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM ES9842 PRO Product Datasheet 73 Register 9: I2S/TDM MASTER CLK CONFIG Bits [7] [6:0] Default 1'b0 7'd3 Bits Mnemonic Description [7] SELECT_I2S_TDM_HALF • 1'b0: Divide by SELECT_I2S_TDM_NUM + 1 (default) • 1'b1: Divide by half of SELECT_I2S_TDM_NUM + 1 Note: Can only produce half of an odd number divide [6:0] SELECT_I2S_TDM_NUM Whole number divide value + 1 for I2S/TDM master encoding clock (SYS_CLK/divide_value). • 7'd0: Whole number divide value + 1 = 1 (default) • 7'd1: Whole number divide value + 1 = 2 • 7'd127: Whole number divide value + 1 = 128 Register 10: TDM CONFIG1 Bits [7:3] [2] [1] [0] Default 5'd0 1'b1 1'b0 1'b1 Bits Mnemonic Description [7:3] TDM_BIT_DELAY Indicates the MSB-2 position of the data from the frame start. Valid from 5'd0 to 5'd31 [2] TDM_VALID_EDGE Sets on which WS edge the frame starts. • 1'b0: Frame starts on posedge of WS • 1'b1: Frame starts on negedge of WS (default) [1] TDM_LJ Sets left-justified mode. • 1'b0: No left-justified (default) • 1'b1: Left-justified [0] ENABLE_TDM_CLK Enables I2S/TDM encoding clock. • 1'b0: I2S/TDM clock disabled • 1'b1: I2S/TDM clock enabled (default) |
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