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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ES9842PRO 数据表(PDF) 60 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 60 Page - ESS Technology,Inc |
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60 / 167 page  CONFIDENTIAL ADVANCE INFORMATION ES9842 PRO Product Datasheet 60 VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM Register Map Addr (Hex) Addr (Dec) Register 7 6 5 4 3 2 1 0 0x00 0 SYS CONFIG SOFT_RESET OUTPUT_SEL RESERVED ENABLE_64FS_ MODE TWO_CH_ MODE MONO_MODE RESERVED 0x01 1 ADC CLOCK CONFIG1 ENABLE_ DATA_IN_CH4 ENABLE_ DATA_IN_CH3 ENABLE_ DATA_IN_CH2 ENABLE_ DATA_IN_CH1 ENABLE_ ADC_CH4 ENABLE_ ADC_CH3 ENABLE_ ADC_CH2 ENABLE_ ADC_CH1 0x02 2 ADC CLOCK CONFIG2 RESERVED SELECT_ ADC_HALF SELECT_ADC_NUM 0x03 3 ADC CLOCK CONFIG3 OUTPUT2_SEL FORCE_ OUTPUT2 INVERT_ FIRST_CLK_ SAMPLE2 SELECT_ IADC_HALF SELECT_IADC_NUM 0x04 4 ADC CLOCK CONFIG4 FORCE_PHASE _CLK_IADC PHASE_CLK_IADC INVERT_ SAMPLE_ CLOCK_CH4 INVERT_ SAMPLE_ CLOCK_CH3 INVERT_ SAMPLE_ CLOCK_CH2 INVERT_ SAMPLE_ CLOCK_CH1 0x05 5 RAW DATA AND SPDIF CONFIG SELECT_RAW_DATA_NUM RAW_DATA_ CLK_DIV2 RAW_DATA_ DDR ENABLE_RAW_ DATA_CLK ENABLE_ SPDIF_CLK RESERVED 0x06 6 DSD CONFIG RESERVED DSD_DDR DSD_MASTER_ MODE ENABLE_DSD_ CLK_CH4 ENABLE_DSD_ CLK_CH3 ENABLE_DSD_ CLK_CH2 ENABLE_DSD_ CLK_CH1 0x07 7 DSD AND I2S/TDM MASTER CLK CONFIG MASTER_WS_SCALE DSD_CLK_DIV2 SELECT_DSD_NUM 0x08 8 I2S/TDM MASTER MODE CONFIG MASTER_ BCK_DIV1 MASTER_ WS_IDLE MASTER_FRAME_LENGTH MASTER_WS_ PULSE_MODE MASTER_ BCK_INVERT MASTER_ WS_INVERT MASTER_ MODE_ENABLE 0x09 9 I2S/TDM MASTER CLK CONFIG SELECT_I2S_T DM_HALF SELECT_I2S_TDM_NUM 0x0A 10 TDM CONFIG1 TDM_BIT_DELAY TDM_ VALID_EDGE TDM_LJ ENABLE_ TDM_CLK 0x0B 11 TDM CONFIG2 TDM_GPIO456 TDM_CASCADE TDM_LENGTH TDM_CH_NUM 0x0C 12 TDM SLOT CONFIG CH1 RESERVED TDM_LINE_SEL_CH1 TDM_SLOT_SEL_CH1 0x0D 13 TDM SLOT CONFIG CH2 RESERVED TDM_LINE_SEL_CH2 TDM_SLOT_SEL_CH2 0x0E 14 TDM SLOT CONFIG CH3 RESERVED TDM_LINE_SEL_CH3 TDM_SLOT_SEL_CH3 0x0F 15 TDM SLOT CONFIG CH4 RESERVED TDM_LINE_SEL_CH4 TDM_SLOT_SEL_CH4 0x10 16 RAW DATA OUTPUT CONFIG RESERVED RAW_DATA_ MIX_DIV2_ CH2_4 RAW_DATA_ MIX_DIV2_ CH1_3 ENABLE_ RAW_DATA_ MIX_CH2_4 ENABLE_ RAW_DATA_ MIX_CH1_3 NEG_ RAW_DATA_ SUB_CH2 NEG_ RAW_DATA_ SUB_CH1 0x11 17 RAW DATA MAPPING RAW_DATA_MAPPING_CH4 RAW_DATA_MAPPING_CH3 RAW_DATA_MAPPING_CH2 RAW_DATA_MAPPING_CH1 0x12 18 PCM DATA OUTPUT MAPPING OUTPUT_MAPPING_CH4 OUTPUT_MAPPING_CH3 OUTPUT_MAPPING_CH2 OUTPUT_MAPPING_CH1 0x13 19 DSD DATA OUTPUT MAPPING DSD_MAPPING_CH4 DSD_MAPPING_CH3 DSD_MAPPING_CH2 DSD_MAPPING_CH1 0x14 20 TPDF DITHER LEVEL RESERVED DITHER_SCALE 0x15 21 DITHER MASK DITHER_MASK 0x16 22 DITHER_MASK 0x17 23 FS GEN PHASE CONTROL DSD_SYNC_TO _1FS FS_PHASE 0x18 - 0x1A 24 - 26 RESERVED RESERVED 0x1B 27 INTERRUPT INTERRUPT_ CLEAR_CH4_ PEAK_DETECT INTERRUPT_ CLEAR_CH3_ PEAK_DETECT INTERRUPT_ CLEAR_CH2_ PEAK_DETECT INTERRUPT_ CLEAR_CH1_ PEAK_DETECT INTERRUPT_ MASK_CH4_ PEAK_DETECT INTERRUPT_ MASK_CH3_ PEAK_DETECT INTERRUPT_ MASK_CH2_ PEAK_DETECT INTERRUPT_ MASK_CH1_ PEAK_DETECT 0x1C 28 SPDIF CONFIG SPDIF_CS 0x1D 29 SPDIF_CS 0x1E 30 SPDIF_CS 0x1F 31 SPDIF_CS 0x20 32 SPDIF_CS 0x21 33 DSD DITHER SCALE & SYNC CONTROL SYNC_ POSEDGE_ FRAME DISABLE_SYNC _REF FORCE_ FIR_SYNC DSD_DITHER_SCALE 0x22 34 SYNC CONTROL AUTO_ADC_ CLKDIV_SYNC AUTO_ CLK_IADC_ PHASE_SYNC AUTO_DSD_ PHASE_SYNC AUTO_WS_ PHASE_SYNC AUTO_ ICG_EN_SYNC AUTO_ ICG_SYNC AUTO_ FIR_SYNC AUTO_ FS_SYNC 0x23 35 ASP1 CONFIG RESERVED SELECT_ASP1_NUM ENABLE_ ASP1_CLK 0x24 36 ASP2 CONFIG RESERVED SELECT_ASP2_NUM ENABLE_ ASP2_CLK 0x25 37 ASP ENABLE & PROGRAM CONTROL ASP2_ COEFF_WE ASP1_ COEFF_WE ASP2_ PROGRAM_WE ASP1_ PROGRAM_WE ASP2_ PROGRAM_EN ASP1_ PROGRAM_EN ENABLE_ASP2 ENABLE_ASP1 0x26 38 ASP PROGRAM ADDR ASP_PROGRAM_ADDR 0x27 39 RESERVED ASP_ PROGRAM_ ADDR 0x28 40 ASP PROGRAM ASP_PROGRAM_IN 0x29 41 RESERVED ASP_PROGRAM_IN 0x2A 42 ASP COEFF ADDR RESERVED ASP_COEFF_ADDR 0x2B 43 ASP COEFF ASP_COEFF_LSB 0x2C 44 ASP_COEFF_LSB 0x2D 45 ASP_COEFF_LSB 0x2E 46 ASP_COEFF_LSB 0x2F 47 ASP_COEFF_MSB 0x30 48 ASP_COEFF_MSB 0x31 49 ASP_COEFF_MSB 0x32 50 ASP_COEFF_MSB 0x33 51 ASP1 CH1 STEP SIZE ASP1_CH1_STEP_SIZE 0x34 52 ASP1 CH2 STEP SIZE ASP1_CH2_STEP_SIZE 0x35 53 ASP2 CH1 STEP SIZE ASP2_CH1_STEP_SIZE 0x36 54 ASP2 CH2 STEP SIZE ASP2_CH2_STEP_SIZE 0x37 55 ASP1 CUSTOM ADDR RESERVED ASP1_CUSTOM_ADDR 0x38 56 ASP1 CUSTOM ADDR2 RESERVED ASP1_CUSTOM_ADDR2 |
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