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ES9842PRO 数据表(PDF) 84 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 84 Page - ESS Technology,Inc |
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84 / 167 page  CONFIDENTIAL ADVANCE INFORMATION ES9842 PRO Product Datasheet 84 VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM Register 23: FS GEN PHASE CONTROL Bits [7] [6:0] Default 1'b0 7'd4 Bits Mnemonic Description [7] DSD_SYNC_TO_1FS In DSD mode, when enabled, DSD logic is sync to an 1FS signal input from GPIO2. When not enabled, DSD logic is sync to DSD clock input from GPIO1. • 1'b0: DSD logic is sync to DSD clock input from GPIO1 (default) • 1'b1: DSD logic is sync to 1FS signal input from GPIO2 [6:0] FS_PHASE Controls phase of the generated FS signals. • Valid from 7'd0 to 7'd127 Note: Should be set to 7'd10 for phase alignment of all sample rates and serial modes Register 26-24: RESERVED Register 27: INTERRUPT Bits [7] [6] [5] [4] [3] [2] [1] [0] Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] INTERRUPT_CLEAR_CH4_PEAK_ DETECT Clears the peak detector interrupt of ADC CH4. • 1'b0: Interrupt held if asserted and not masked (default) • 1'b1: Interrupt cleared [6] INTERRUPT_CLEAR_CH3_PEAK_ DETECT Clears the peak detector interrupt of ADC CH3. • 1'b0: Interrupt held if asserted and not masked (default) • 1'b1: Interrupt cleared [5] INTERRUPT_CLEAR_CH2_PEAK_ DETECT Clears the peak detector interrupt of ADC CH2. • 1'b0: Interrupt held if asserted and not masked (default) • 1'b1: Interrupt cleared [4] INTERRUPT_CLEAR_CH1_PEAK_ DETECT Clears the peak detector interrupt of ADC CH1. • 1'b0: Interrupt held if asserted and not masked (default) • 1'b1: Interrupt cleared |
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