ES9842PRO datasheet(69/167 Pages) ESS

69 / 167 page

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9842 PRO Product Datasheet

Bits

[7:6]

[5]

[4]

[3]

[2]

[1:0]

Default

2'd0

1'b0

2'd0

Bits

Mnemonic

Description

[7:6]

SELECT_RAW_DATA_NUM

Whole number divide value + 1 for raw data clock

(SYS_CLK/divide_value). When SELECT_RAW_DATA_NUM is

larger than 0, the divided clock is not a 50% duty cycle clock.

• 2'd0: Whole number divide value + 1 = 1 (default)

• 2'd1: Whole number divide value + 1 = 2

• 2'd2: Whole number divide value + 1 = 3

• 2'd3: Whole number divide value + 1 = 4

[5]

RAW_DATA_CLK_DIV2

Further divides the raw data clock by 2 (after divided by

SELECT_RAW_DATA_NUM+1) to create a 50% duty cycle raw data

clock.

• 1'b0: No divide (default)

• 1'b1: Further divides the raw data clock by 2

[4]

RAW_DATA_DDR

Enables raw data double-data-rate (DDR) output.

In the DDR mode, raw data is valid on both pos/neg edges of raw

data clock.

Otherwise, raw data is valid only on positive edge of raw data clock.

• 1'b0: Double-data-rate disabled (default)

• 1'b1: Double-data-rate enabled

[3]

ENABLE_RAW_DATA_CLK

Enables raw data clock.

• 1'b0: Raw data clock disabled (default)

• 1'b1: Raw data clock enabled

[2]

ENABLE_SPDIF_CLK

Enables SPDIF encoding clock.

• 1'b0: SPDIF clock disabled (default)

• 1'b1: SPDIF clock enabled

[1:0]

RESERVED

ES9842PRO 数据表(PDF) 69 Page - ESS Technology,Inc

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