ES9842PRO datasheet(6/167 Pages) ESS

6 / 167 page

CONFIDENTIAL ADVANCE INFORMATION

ES9842 PRO Product Datasheet

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

List of Figures

Figure 1 - ES9842 PRO Block Diagram................................................................................................................................... 8

Figure 2 - 40 QFN Pinout......................................................................................................................................................... 9

Figure 3 - Digital signal path .................................................................................................................................................. 12

Figure 4 - Connection for TDM Cascade Mode ..................................................................................................................... 16

Figure 5 - Channel cascading and data line composition in TDM cascade mode for 8ch and 16ch TDM data lines ............. 17

Figure 6 - Connection for Parallel TDM / PCM....................................................................................................................... 17

Figure 7 – Channel(slot), mapping and data line composition for TDM in parallel mode ....................................................... 18

Figure 8 – Minimum Phase 64FS Frequency Response ....................................................................................................... 34

Figure 9 – Minimum Phase 64FS Impulse Response............................................................................................................ 34

Figure 10 - ES9842 PRO Clock Distribution .......................................................................................................................... 35

Figure 11 - Audio Interface Timing Requirements ................................................................................................................. 50

Figure 12 - 45/49MHz MCLK with BCK Phase Relationship.................................................................................................. 50

Figure 13 – 22/25MHz MCLK with BCK Phase Relationship................................................................................................. 51

Figure 14 - Recommended Power up/down Sequences........................................................................................................ 53

Figure 15 - I2C Slave Control Interface Timing Diagram........................................................................................................ 58

Figure 16 - SPI command timing diagrams............................................................................................................................ 59

Figure 17 - ES9842PRO Reference Schematic................................................................................................................... 150

Figure 18 - Reference Schematic ADC Input Stage for Single Ended (S/E) and Differential Input ...................................... 151

Figure 19 - ES9311Q Reference Voltage Regulator Schematic .......................................................................................... 151

Figure 20 - 40 QFN Package Dimensions ........................................................................................................................... 154

Figure 21 - ES9842 PRO QFN Marking............................................................................................................................... 155

Figure 22 - IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1) ............................................................................... 156

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