ES9842PRO datasheet(71/167 Pages) ESS

71 / 167 page

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9842 PRO Product Datasheet

Bits

[7:5]

[4]

[3:0]

Default

3'd0

1'b0

4'd0

Bits

Mnemonic

Description

[7:5]

MASTER_WS_SCALE

In I2S/TDM master mode, tunes master BCK/WS ratio by scaling

master WS. It allows more TDM slots in a fixed frame.

• 3'd0: No scale (default)

• 3'd1: Scale down WS by 2

• 3'd2: Scale down WS by 4

• 3'd3: Scale down WS by 8

• 3'd4: Scale down WS by 16

• others: Reserved

[4]

DSD_CLK_DIV2

Further divides the DSD clock by 2 (after divided by

SELECT_DSD_NUM+1) to create a 50% duty cycle DSD clock.

• 1'b0: No divide (default)

• 1'b1: Further divides the DSD clock by 2

[3:0]

SELECT_DSD_NUM

Whole number divide value + 1 for DSD clock

(SYS_CLK/divide_value). When SELECT_DSD_NUM is larger than

0, the divided clock is not a 50% duty cycle clock.

• 4'd0: Whole number divide value + 1 = 1 (default)

• 4'd1: Whole number divide value + 1 = 2

• 4'd15: Whole number divide value + 1 = 16

ES9842PRO 数据表(PDF) 71 Page - ESS Technology,Inc

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