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数据搜索系统，热门电子元器件搜索 |
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ES9842PRO 数据表(PDF) 65 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 65 Page - ESS Technology,Inc |
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65 / 167 page  VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM ES9842 PRO Product Datasheet 65 Register 1: ADC CLOCK CONFIG1 Bits [7] [6] [5] [4] [3] [2] [1] [0] Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] ENABLE_DATA_IN_CH4 Enables Ch4 data input clock (before decimation path) for data mixing. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [6] ENABLE_DATA_IN_CH3 Enables Ch3 data input clock (before decimation path) for data mixing. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [5] ENABLE_DATA_IN_CH2 Enables Ch2 data input clock (before decimation path) for data mixing. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [4] ENABLE_DATA_IN_CH1 Enables Ch1 data input clock (before decimation path) for data mixing. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [3] ENABLE_ADC_CH4 Enables ADC Ch4 decimation path clock. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [2] ENABLE_ADC_CH3 Enables ADC Ch3 decimation path clock. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [1] ENABLE_ADC_CH2 Enables ADC Ch2 decimation path clock. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled [0] ENABLE_ADC_CH1 Enables ADC Ch1 decimation path clock. • 1'b0: Clock disabled (default) • 1'b1: Clock enabled |
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