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ES9842PRO 数据表(PDF) 131 Page - ESS Technology,Inc |
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ES9842PRO 数据表(HTML) 131 Page - ESS Technology,Inc |
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131 / 167 page  VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM ES9842 PRO Product Datasheet 131 ADC CH3 Registers Register 135: ADC CH3 DATAPATH CONTROL Bits [7] [6] [5:3] [2] [1] [0] Default 1'b0 1'b0 3'b000 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] ADC3_BYPASS_FIR2X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFIR_2x [6] ADC3_BYPASS_FIR4X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFIR_4x [5:3] RESERVED NA [2] ADC3_ENABLE_DC_BLOCKING Enables DC blocking path. • 1'b0: Disabled (default) • 1'b1: Enabled [1] RESERVED NA [0] ADC3_NEG_SEL Inverts data input from analog ADC. • 1'b0: No inversion (default) • 1'b1: Inverts input data Register 136: ADC CH3 THD COMP CONFIG Bits [7:2] [1] [0] Default 6'd0 1'b0 1'b0 Bits Mnemonic Description [7:2] ADC3_CORRECTION_ADDR Selects the address when writing the THD compensation RAM. [1] ADC3_CORRECTION_WE Enables writing to the THD compensation RAM. • 1'b0: Writing disabled (default) • 1'b1: Writing enabled [0] ADC3_ENABLE_THD_COMP Enables the THD compensation on ADC CH3. • 1'b0: Disabled and bypassed (default) • 1'b1: Enabled |
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