ST92F124 datasheet(343/429 Pages) STMICROELECTRONICS

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CONTROLLER AREA NETWORK (bxCAN)

CONTROLLER AREA NETWORK (Cont’d)

10.10.8 Register Description

10.10.8.1 Control and Status Registers

CAN MASTER CONTROL REGISTER (CMCR)

Reset Value: 0000 0010 (02h)

Bit 7 = TTCM Time Triggered Communication

Mode

- Read/Set/Clear

0: Time Triggered Communication mode disabled.

1: Time Triggered Communication mode enabled

Note: For more information on Time Triggered

Communication mode, please refer to Section

10.10.5.2 Time Triggered Communication Mode.

Bit 6 = ABOM Automatic Bus-Off Management

- Read/Set/Clear

This bit controls the behaviour of the CAN hard-

ware on leaving the Bus-Off state.

0: The Bus-Off state is left on software request,

once 128 x 11 recessive bits have been moni-

tored and the software has first set and cleared

the INRQ bit of the CMCR register.

1: The Bus-Off state is left automatically by hard-

ware once 128 x 11 recessive bits have been

monitored.

For detailed information on the Bus-Off state

please refer to Section 10.10.5.6 Error Manage-

ment.

Bit 5 = AWUM Automatic Wake-Up Mode

- Read/Set/Clear

This bit controls the behaviour of the CAN hard-

ware on message reception during sleep mode.

0: The sleep mode is left on software request by

clearing the SLEEP bit of the CMCR register.

1: The sleep mode is left automatically by hard-

ware on CAN message detection. The SLEEP

bit of the CMCR register and the SLAK bit of the

CMSR register are cleared by hardware.

Bit 4 = NART No Automatic Retransmission

- Read/Set/Clear

0: The CAN hardware will automatically retransmit

the message until it has been successfully

transmitted according to the CAN standard.

1: A message will be transmitted only once, inde-

pendently of the transmission result (successful,

error or arbitration lost).

Bit 3 = RFLM Receive FIFO Locked Mode

- Read/Set/Clear

0: Receive FIFO not locked on overrun. Once a re-

ceive FIFO is full the next incoming message

will overwrite the previous one.

1: Receive FIFO locked against overrun. Once a

receive FIFO is full the next incoming message

will be discarded.

Bit 2 = TXFP Transmit FIFO Priority

- Read/Set/Clear

This bit controls the transmission order when sev-

eral mailboxes are pending at the same time.

0: Priority driven by the identifier of the message

1: Priority driven by the request order (chronologi-

cally)

Bit 1 = SLEEP Sleep Mode Request

- Read/Set/Clear

This bit is set by software to request the CAN hard-

ware to enter the sleep mode. Sleep mode will be

entered as soon as the current CAN activity (trans-

mission or reception of a CAN frame) has been

completed.

This bit is cleared by software to exit sleep mode.

This bit is cleared by hardware when the AWUM

bit is set and a SOF bit is detected on the CAN Rx

signal.

Bit 0 = INRQ Initialization Request

- Read/Set/Clear

The software clears this bit to switch the hardware

into normal mode. Once 11 consecutive recessive

bits have been monitored on the Rx signal the

CAN hardware is synchronized and ready for

transmission and reception. Hardware signals this

event by clearing the INAK bit if the CMSR regis-

ter.

Software sets this bit to request the CAN hardware

to enter initialization mode. Once software has set

the INRQ bit, the CAN hardware waits until the

current CAN activity (transmission or reception) is

completed before entering the initialization mode.

Hardware signals this event by setting the INAK bit

in the CMSR register.

TTCM ABOM AWUM NART

RFLM

TXFP SLEEP INRQ

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