ST92F124 datasheet(344/429 Pages) STMICROELECTRONICS

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CONTROLLER AREA NETWORK (bxCAN)

CONTROLLER AREA NETWORK (Cont’d)

CAN MASTER STATUS REGISTER (CMSR)

Reset Value: 0000 0010 (02h)

Note: To clear a bit of this register the software

must write this bit with a one.

Bit 7:4 = Reserved. Forced to 0 by hardware.

Bit 5 = REC Receive

- Read

The CAN hardware is currently receiver.

Bit 4 = TRAN Transmit

- Read

The CAN hardware is currently transmitter.

Bit 3 = WKUI Wake-Up Interrupt

- Read/Clear

This bit is set by hardware to signal that a SOF bit

has been detected while the CAN hardware was in

sleep mode. Setting this bit generates a status

change interrupt if the WKUIE bit in the CIER reg-

ister is set.

This bit is cleared by software.

Bit 2 = ERRI Error Interrupt

- Read/Clear

This bit is set by hardware when a bit of the CESR

has been set on error detection and the corre-

sponding interrupt in the CEIER is enabled. Set-

ting this bit generates a status change interrupt if

the ERRIE bit in the CIER register is set.

This bit is cleared by software.

Bit 1 = SLAK Sleep Acknowledge

- Read

This bit is set by hardware and indicates to the

software that the CAN hardware is now in sleep

mode. This bit acknowledges the sleep mode re-

quest from the software (set SLEEP bit in CMCR

This bit is cleared by hardware when the CAN

hardware has left sleep mode. Sleep mode is left

when the SLEEP bit in the CMCR register is

cleared. Please refer to the AWUM bit of the

CMCR register description for detailed information

for clearing SLEEP bit.

Bit 0 = INAK Initialization Acknowledge

- Read

This bit is set by hardware and indicates to the

software that the CAN hardware is now in initiali-

zation mode. This bit acknowledges the initializa-

tion request from the software (set INRQ bit in

CMCR register).

This bit is cleared by hardware when the CAN

hardware has left the initialization mode and is

now synchronized on the CAN bus. To be syn-

chronized the hardware has to monitor a se-

quence of 11 consecutive recessive bits on the

CAN RX signal.

CAN TRANSMIT STATUS REGISTER (CTSR)

Read / Write

Reset Value: 0000 0000 (00h)

Note: To clear a bit of this register the software

must write this bit with a one.

Bit 7 = Reserved. Forced to 0 by hardware.

Bit 6 = TXOK2 Transmission OK for mailbox 2

- Read

This bit is set by hardware when the transmission

request on mailbox 2 has been completed suc-

cessfully. Please refer to Figure 147.

This bit is cleared by hardware when mailbox 2 is

requested for transmission or when the software

clears the RQCP2 bit.

Bit 5 = TXOK1 Transmission OK for mailbox 1

- Read

This bit is set by hardware when the transmission

request on mailbox 1 has been completed suc-

cessfully. Please refer to Figure 147.

This bit is cleared by hardware when mailbox 1 is

requested for transmission or when the software

clears the RQCP1 bit.

REC

TRAN

WKUI

ERRI

SLAK

INAK

TXOK2 TXOK1 TXOK0

RQCP2 RQCP1 RQCP0

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