MPC5553_07 datasheet(21/66 Pages) FREESCALE

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Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 2.0

Freescale Semiconductor

CLKOUT period jitter,12, 13

measured at fSYS maximum

peak-to-peak jitter

(clock edge to clock edge)

Long term jitter

(averaged over 2 ms interval)

CJITTER

—

5.0

0.01

fCLKOUT

Frequency modulation range limit 14

(do not exceed fsys maximum)

CMOD

0.8

2.4

%fSYS

ICO frequency

fico = [ fref × (MFD + 4) ] ÷ (PREDIV + 1)

fico

fsys

MHz

Predivider output frequency (to PLL)

fPREDIV

4fMAX

MHz

1 All internal registers retain data at 0 Hz.

2 Up to the maximum frequency rating of the device (refer to Table 1).

3 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into

self-clocked mode.

4 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f

LOR. SCM frequency is

measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.

NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.

5 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or

resonators). (Vextal – Vxtal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.

6 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or

resonators). (Vxtal –Vextal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.

7 I

xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

8 C

PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal

startup time.

10 PLL is operating in 1:1 PLL mode.

11 V

DDE = 3.0–3.6 V

12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage

for a given interval. CLKOUT divider is set to divide-by-two.

13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).

14 Modulation depth selected must not result in f

sys value greater than the fsys maximum specified value.

15 f

sys = fico ÷ (2

RFD).

Table 12. FMPLL Electrical Specifications (continued)

(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)

Spec

Characteristic

Symbol

Minimum

Maximum

Unit

MPC5553 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

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