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MPC5553 数据表(PDF) 40 Page - Freescale Semiconductor, Inc |
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MPC5553 数据表(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 66 page  MPC5553 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics Freescale Semiconductor 40 Figure 19. DSPI Classic SPI Timing—Master, CPHA = 0 1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. 2 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. 3 The actual minimum SCK cycle time is limited by pad performance. 4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. 5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 6 This number is calculated using the SMPL_PT bit field in DSPI_MCR set to 0b10. Data Last data First data First data Data Last data SIN SOUT PCSx SCK output 4 9 12 1 11 10 4 SCK output (CPOL=0) (CPOL=1) 3 2 |
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