MPC5553_07 datasheet(47/66 Pages) FREESCALE

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Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 2.0

Freescale Semiconductor

3.14.2

MII FEC Transmit Signal Timing

FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK

The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one

percent. There is no minimum frequency requirement. In addition, the processor clock frequency must

exceed twice the FEC_TX_CLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER) can be programmed to transition

from either the rising- or falling-edge of TX_CLK, and the timing is the same in either case. These options

allow the use of non-compliant MII PHYs.

Refer to the Fast Ethernet Controller (FEC) chapter of the device reference manual for details of this option

and how to enable it.

Table 29 lists MII FEC transmit channel timings.

Figure 30 shows MII FEC transmit signal timings listed in Table 29.

Figure 30. MII FEC Transmit Signal Timing Diagram

Table 29. MII FEC Transmit Signal Timing

Spec

Characteristic

Min

Max

Unit

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

—

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

—

FEC_TX_CLK pulse-width high

35%

65%

FEC_TX_CLK period

FEC_TX_CLK pulse-width low

35%

65%

FEC_TX_CLK period

FEC_TX_CLK (input)

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

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