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MPC5553 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC5553 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 66 page  Electrical Characteristics MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 39 3.13.7 eMIOS (MTS) Timing 3.13.8 DSPI Timing Table 25. MTS Timing1 1 MTS timing specified at F SYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. Spec Characteristic Symbol Min Max Unit 1 eMIOS (MTS) input pulse width tMIPW 4— tCYC 2 eMIOS (MTS) output pulse width tMOPW 1— tCYC Table 26. DSPI Timing1 Spec Characteristic Symbol 80 MHz 112 MHz 132 MHz Unit Min Max Min Max Min Max 1 SCK cycle time2,3 tSCK 25 ns 2.9 ms 17.9 ns 2.0 ms 15.2 ns 1.7 ms — 2 PCS to SCK delay4 tCSC 23 — 15 — 13 — ns 3 After SCK delay5 tASC 22 — 14 — 12 — ns 4 SCK duty cycle tSDC (tSCK ÷ 2) – 2 ns (tSCK ÷ 2) + 2 ns —— — — ns 5 Slave access time (SS active to SOUT driven) tA — 25 — 25 — 25 ns 6 Slave SOUT disable time (SS inactive to SOUT Hi-Z, or invalid) tDIS — 25 — 25 — 25 ns 7 PCSx to PCSS time tPCSC 4— 4 — 4 — ns 8PCSS to PCSx time tPASC 5— 5 — 5 — ns 9 Data setup time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) tSUI 20 2 –4 20 — — — — 20 2 3 20 — — — — 20 2 6 20 — — — — ns ns ns ns 10 Data hold time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) tHI –4 7 21 –4 — — — — –4 7 14 –4 — — — — –4 7 12 –4 — — — — ns ns ns ns 11 Data valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tSUO — — — — 5 25 18 5 — — — — 5 25 14 5 — — — — 5 25 13 5 ns ns ns ns 12 Data hold time for outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tHO –5 5.5 8 –5 — — — — –5 5.5 4 –5 — — — — –5 5.5 3 –5 — — — — ns ns ns ns |
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