MPC5553_07 datasheet(22/66 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 2.0

Electrical Characteristics

Freescale Semiconductor

3.10

eQADC Electrical Characteristics

Table 13. eQADC Conversion Specifications (Operating)

Spec

Characteristic

Symbol

Minimum

Maximum

Unit

ADC clock (ADCLK) frequency1

1 Conversion characteristics vary with F

ADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The

maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a

maximum 16 factor.

FADCLK

112

MHz

Conversion cycles

Differential

Single ended

13 + 2 (15)

14 + 2 (16)

13 + 128 (141)

14 + 128 (142)

ADCLK

cycles

Stop mode recovery time2

2 Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform

conversions.

TSR

—

μs

Resolution3

3 At V

RH – VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.

—1.25

—

INL: 6 MHz ADC clock

INL6

–4

Counts3

INL: 12 MHz ADC clock

INL12

–8

Counts

DNL: 6 MHz ADC clock

DNL6

–3 4

4 Guaranteed 10-bit monotonicity.

3 4

Counts

DNL: 12 MHz ADC clock

DNL12

–6 4

Counts

Offset error with calibration

OFFWC

–4 5

5 The absolute value of the offset error without calibration

≤ 100 counts.

4 5

Counts

Full-scale gain error with calibration

GAINWC

–8 6

6 The absolute value of the full scale gain error without calibration

≤ 120 counts.

8 6

Counts

Disruptive input injection current 7, 8, 9, 10

7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than

VRH, and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample

amplifier. Other channels are not affected by non-disruptive conditions.

8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not

affect device reliability or cause permanent damage.

9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.

10 Condition applies to two adjacent pads on the internal pad.

IINJ

–1

Incremental error due to injection current. All channels have

same 10 k

Ω < Rs <100 kΩ

Channel under test has Rs = 10 k

Ω,

IINJ = IINJMAX, IINJMIN

EINJ

–4

Counts

Total Unadjusted Error for single ended conversions with

calibration11, 12, 13, 14, 15

11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.

12 TUE does not apply to differential conversions.

13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.

14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).

15 Depending on the input impedance, the analog input leakage current (DC Electrical specification 35a) can affect the actual

TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].

TUE

–4

Counts

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