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MPC5553 数据表(PDF) 48 Page - Freescale Semiconductor, Inc |
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MPC5553 数据表(HTML) 48 Page - Freescale Semiconductor, Inc |
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48 / 66 page ![]() MPC5553 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics Freescale Semiconductor 48 3.14.3 MII FEC Asynchronous Inputs Signal Timing FEC_CRS and FEC_COL Table 30 lists MII FEC asynchronous input signal timing. Figure 31 shows MII FEC asynchronous input timing listed in Table 30. Figure 31. MII FEC Asynchronous Inputs Timing Diagram 3.14.4 MII FEC Serial Management Channel Timing FEC_MDIO and FEC_MDC Table 31 lists MII FEC serial management channel timings. The FEC functions correctly with a maximum FEC_MDC frequency of 2.5 MHz. Figure 32 shows MII FEC serial management channel timings listed in Table 31. Table 30. MII FEC Asynchronous Inputs Signal Timing Spec Characteristic Min Max Unit 9 FEC_CRS, FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period Table 31. MII FEC Serial Management Channel Timing Spec Characteristic Min Max Unit 10 FEC_MDC falling-edge to FEC_MDIO output invalid (minimum propagation delay) 0— ns 11 FEC_MDC falling-edge to FEC_MDIO output valid (maximum propagation delay) —25 ns 12 FEC_MDIO (input) to FEC_MDC rising-edge setup 10 — ns 13 FEC_MDIO (input) to FEC_MDC rising-edge hold 0 — ns 14 FEC_MDC pulse-width high 40% 60% FEC_MDC period 15 FEC_MDC pulse-width low 40% 60% FEC_MDC period FEC_CRS, FEC_COL M9 |
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