MPC5553_07 datasheet(45/66 Pages) FREESCALE

45 / 66 page

Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 2.0

Freescale Semiconductor

3.13.9

eQADC SSI Timing

Figure 28. EQADC SSI Timing

Table 27. EQADC SSI Timing Characteristics (Pads at 3.3 V or 5.0 V)

CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.

Spec

Rating

Symbol

Minimum

Typical

Maximum

Unit

FCK period (tFCK = 1 ÷ fFCK)

1, 2

1 SS timing specified at F

SYS = 132 MHz, VDD = 1.35–1.65 V, VDDEH = 3.0–5.5 V, VDD33 and VDDSYN = 3.0–3.6 V,

TA = TL to TH, and CL = 50 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master

pad delays, and slave pad delays.

2 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

tFCK

2—

tSYS_CLK

Clock (FCK) high time

tFCKHT

tSYS_CLK − 6.5

—

× (t

SYS_CLK + 6.5)

Clock (FCK) low time

tFCKLT

tSYS_CLK − 6.5

—

× (t

SYS_CLK + 6.5)

SDS lead / lag time

tSDS_LL

–7.5

—

+7.5

SDO lead / lag time

tSDO_LL

–7.5

—

+7.5

EQADC data setup time (inputs)

tEQ_SU

—

EQADC data hold time (inputs)

tEQ_HO

1—

—

1st (MSB)

2nd

25th

26th

1st (MSB) 2nd

25th

26th

FCK

SDS

SDO

External device data sample at

SDI

EQADC data sample at

FCK falling-edge

FCK rising-edge

MPC5553 数据表(PDF) 45 Page - Freescale Semiconductor, Inc

MPC5553 数据表(HTML) 45 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载