ADIN1100CCPZ-R7 datasheet(30/80 Pages) AD

30 / 80 page

Data Sheet

ADIN1100

ON-CHIP DIAGNOSTICS

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Rev. B | 30 of 80

Figure 14. ADIN1100 Loopback Modes

FRAME GENERATOR AND CHECKER

Overview

The ADIN1100 can be configured to generate frames and to check

received frames (see Figure 15). The generating and checking

functions can be used together or independently. If the ADIN1100

transmitted frames are looped back at the remote end, the frame

checker can be used to check the echoed self generated frames.

Frame Generator

When the frame generator is enabled, the MAC interface is ignored

and the frame generator data is used for transmission on the MDI

pins. To use the frame generator, the diagnostic clock must also

be enabled using the CRSM_DIAG_CLK_EN bit (see the CRSM

Diagnostics Clock Control Register section).

The frame generator control registers configure the type of frames

to be sent (for example, random data, all 1s), the frame length, and

the number of frames to be generated.

The generation of the requested frames starts by enabling the

frame generator by setting the FG_EN bit (see the Frame Genera-

tor Enable Register section).

When the generation of the frames is completed, the frame gener-

ator done bit, FG_DONE, is set (see the Frame Generator Done

Frame Checker

The frame checker is enabled by setting the frame checker enable

bit, FC_EN (see the Frame Checker Enable Register section). The

frame checker can be configured to check and analyze received

frames from either the MAC interface or the PHY using the frame

checker transmit select bit, FC_TX_SEL (see theFrame Checker

Transmit Select Register section). The frame checker reports the

number of frames received, cyclic redundancy check (CRC) errors,

and various frame errors. The frame checker frame counter regis-

ters and the frame checker error counter registers count these

events.

Error Counters

The frame checker counts the number of CRC errors, and

these errors are reported in the receive error counter register

(RX_ERR_CNT). To ensure synchronization between the frame

checker error counter and frame checker frame counters, all of

the counters are latched when the receive error counter register is

read. Therefore, when using the frame checker, read the receive

error counter first, and then read all other frame counters and error

counters. A latched copy of the receive frame counter register is

available in FC_FRM_CNT_H (see the Frame Checker Count High

Count Low Register section).

In addition to CRC errors, the frame checker counts frame length

errors, frame alignment errors, symbol errors, oversized frames

errors, and undersized frame errors.

The frame checker also counts frames with an odd number of

nibbles in the frame, and counts packets with an odd number of

nibbles in the preamble.

The frame checker also counts the number of false carrier events,

which is a count of the number of times the bad start of stream

delimiter (SSD) state is entered.

FRAME GENERATOR AND CHECKER LINK

TEST

Using the ADIN1100 and a second PHY device, the user can

configure a convenient, self contained validation setup of the

PHY to PHY connection. Figure 15 shows an overview of how

each PHY is configured. An external cable is connected between

both devices, and PHY 1 is generating frames using the frame

generator. PHY 2 has MAC interface remote loopback enabled

using MAC_IF_REM_LB_EN (see the MAC Interface Loopbacks

Configuration Register section).

1. The PHY 1 frames (frame generator) are sent over the

10BASE-T1L single pair cable.

2. PHY 2 receives frames on the PHY 2 MDI pins.

3. The PHY 2 MAC interface loops the frame back.

4. The PHY 2 frames (looped back) are sent over the 10BASE-

T1L single pair cable.

5. PHY 1 receives the PHY 2 frames (looped back) on the MDI

pins.

6. The PHY 1 frame checker checks the received frames.

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