ADIN1100CCPZ-R7 datasheet(32/80 Pages) AD

32 / 80 page

Data Sheet

ADIN1100

ON-CHIP DIAGNOSTICS

analog.com

Rev. B | 32 of 80

TEST MODES

The ADIN1100 provides several test modes as described in Sub-

clause 146.5.2 from the IEEE 802.3cgTM-2019 standard that allows

testing of the transmitter waveform, distortion, jitter, and droop.

These test modes change only the data symbols provided to the

transmitter circuitry and do not alter the electrical and jitter charac-

teristics of the transmitter and receiver from the normal operation.

Additionally, the ADIN1100 supports the transmit disable mode as

described in Subclause 45.2.1.186a.2.

Table 24. ADIN1100 Test Modes Summary

Test Mode

Description

PMA Test Modes

(Subclause 146.5.2)

Test Mode 1

Transmitter output voltage and timing jitter test mode.

When this mode is selected, the ADIN1100 repeatedly

transmits the data symbol sequence (+1, –1).

Test Mode 2

Transmitter output droop test mode. In this mode, the

ADIN1100 transmits ten +1 symbols followed by ten

−1 symbols. This sequence is repeated indefinitely.

Test Mode 3

Normal operation in idle mode test mode. In this

mode, the ADIN1100 transmits as in non test opera-

tion and in the master data mode with the data set to

normal interframe idle signals.

Transmit Disable Mode

(Subclause 45.2.1.186a.2)

Both transmit and receive paths act like in normal

operation mode but only transmit 0 symbols. This

mode can be used to measure the MDI return loss

specified in Subclause 146.8.3.

Enable the PMA Test Mode 1 to Test Mode 3

The ADIN1100 can be configured in one of the PMA test modes

(Test Mode 1 to Test Mode 3) using the following procedure:

1. Enter software power-down mode by writing a 1 to the

CRSM_SFT_PD bit in the CRSM_SFT_PD_CNTRL register

(see the Software Power-Down Control Register section).

2. Check that the ADIN1100 has entered software power-down

mode by reading the CRSM_SFT_PD_RDY bit in the

CRSM_STAT register (see the System Status Register).

3. Disable autonegotiation by writing a 0 to the AN_EN bit in

the AN_CONTROL register (see the BASE-T1 Autonegotiation

Control Register section).

4. Set autonegotiation forced mode by writing a 1 to the

AN_FRC_MODE_EN bit in the AN_FRC_MODE_EN register

(see the Autonegotiation Forced Mode Enable Register).

5. Select the desired test mode by writing the appropri-

ate value to the B10L_TX_TEST_MODE bits in the

B10L_TEST_MODE_CNTRL register (see the 10BASE-T1L

Test Mode Control Register section). Table 25 outlines the bit

settings for each PMA test mode.

6. Exit software power-down mode by writing 0 to the

CRSM_SFT_PD bit in the CRSM_SFT_PD_CNTRL register

(see the Software Power-Down Control Register section).

Table 25. PMA Test Modes Configuration

PMA Test Mode

B10L_TX_TEST_MODE, Bits[15:13] (Binary)

Test Mode 1

001

Test Mode 2

010

Test Mode 3

011

Enable Transmit Disable Mode

System Status RegisterThe ADIN1100 can be configured in trans-

mit disable mode using the following procedure:

1. Enter software power-down mode by writing a 1 to the

CRSM_SFT_PD bit in the CRSM_SFT_PD_CNTRL register

(see the Software Power-Down Control Register section).

2. Check that the ADIN1100 has entered the software power-

down mode by reading the CRSM_SFT_PD_RDY bit in the

CRSM_STAT register (see the System Status Register section).

3. Disable autonegotiation by writing a 0 to the AN_EN bit in

the AN_CONTROL register (see the BASE-T1 Autonegotiation

Control Register section).

4. Set autonegotiation forced mode by writing a 1 to the

AN_FRC_MODE_EN bit in the AN_FRC_MODE_EN register

(see the Autonegotiation Forced Mode Enable Register sec-

tion).

5. Set the transmit disable mode by writing a 1 to the

B10L_TX_DIS_MODE_EN bit in the B10L_PMA_CNTRL regis-

ter (see the 10BASE-T1L PMA Control Register section).

6. Exit software power-down mode by writing 0 to the

CRSM_SFT_PD bit in the CRSM_SFT_PD_CNTRL register

(see the Software Power-Down Control Register section).

TIME DOMAIN REFLECTOMETRY (TDR)

Given that the 10BASE-T1L compliant PHY enables communication

over long cables, debugging a faulty cable can become costly and

difficult without the right tools. To help with this, Analog Devices

10BASE-T1L products provide a TDR engine that enables cable

fault detection, distance to fault, and cable length estimation.

The diagnostics solution is the combination of a highly accurate

on-chip TDR engine and a set of algorithms that run on a host

microcontroller, allowing maximum flexibility for a wide variety of

cables and more advanced cable diagnostic capabilities.

Figure 16. ADIN1100 TDR Engine

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