ADIN1100CCPZ-R7 datasheet(40/80 Pages) AD

40 / 80 page

Data Sheet

ADIN1100

MDIO INTERFACE

analog.com

Rev. B | 40 of 80

RECOMMENDED REGISTER OPERATION

Many of the ADIN1100 registers are defined and compliant with

the IEEE 802.3 standard. The register behaviors defined by the

standard are not always obvious and are described in the Latch

Low Registers, IEEE Duplicated Registers, and Read Modify Write

Operation sections, including the recommended operation and use

of the registers.

Latch Low Registers

The IEEE Standard 802.3-2018 requires certain MDIO accessi-

ble registers to exhibit latch low behavior. This behavior allows

software that only intermittently reads these registers to detect

conditions that may be transitory or short lived. For example, the

AN_LINK_STATUS bit is required to latch low. When the device

exits from a reset or power-down state, the latching condition is

not active and the value of the AN_LINK_STATUS bit reflects the

current status of the link. However, if the link comes up and then

drops, the latching condition becomes active. In this case, the

AN_LINK_STATUS bit reads as 0 even if the link has come back up

again in the interim. The latching condition is only cleared after the

AN_LINK_STATUS bit is read to ensure that software has had the

opportunity to observe that the link dropped.

This latch low behavior means that the software must perform two

reads of the AN_LINK_STATUS bit back to back to determine the

current status of the link. The first read is needed to clear any active

latching condition.

It is important that the software take account of the interaction

between MDIO accessible bits that share a register address.

For example, the AN_PAGE_RX and AN_LINK_STATUS bits re-

side at the same register address. As a result, reading the

AN_PAGE_RX bit clears any active latching condition associated

with the AN_LINK_STATUS bit.

IEEE Duplicated Registers

IEEE Standard 802.3-2018 covers a wide range of definitions and

speeds from 10 Mbps to 40 Gbps and higher, and includes an

extensive number of clauses. Many of the registers defined by this

standard are associated with various clauses, and different PHYs

may include different clauses and/or combinations of clauses. Thus,

the registers for common functions like software reset, software

power-down, and loopback tend to be implemented in multiple

clauses.

In the ADIN1100, the physical implementation of these registers is

in a single location, but they can be accessed at multiple address-

es. For example, the software reset bit can be read or written in

all the IEEE MMD locations and vendor specific register locations

listed in Table 36.

Table 36. Software Reset Bit Access in IEEE MMD Locations

Device

Address

Address Bit Name

Bit

PMA/PMD Control 1

(IEEE 802.3)

0x01

0x0000

Reset

(IEEE 802.3)

10BASE-T1L PMA Control

(IEEE 802.3.cg)

0x01

0x08F6

PMA reset

(IEEE 802.3.cg)

PCS Control 1

(IEEE 802.3)

0x03

0x0000

Reset

(IEEE 802.3)

10BASE-T1L PCS Control

(IEEE 802.3.cg)

0x03

0x08E6

PCS reset

(IEEE 802.3.cg)

Software Reset

(ADIN1100)

0x1E

0x8810

CRSM_SFT_RST

(ADIN1100)

In this example, these locations are the PMA/PMD, PCS, autonego-

tiation, and Vendor Specific 1 device address locations (per Table

33).

The ADIN1100 has multiple address locations for the same register

to match the IEEE standard.

The ADIN1100 data sheet only mentions a single recommended

address location for each of these IEEE registers to simplify the

operation and use of the device. In general, the registers introduced

in the 802.3cg (10BASE-T1L) section of the standard are recom-

mended over older (equivalent) registers. Registers in a vendor

specific address are recommended, in particular where a register

brings a number of useful IEEE register bits into a single register

address. The ADIN1100 correctly responds to register accesses to

all the IEEE register address locations covered by the 10BASE-T1L

standard when the start-up sequence is complete after power-up,

hardware reset, or software reset.

Read Modify Write Operation

It is strongly recommended that all register write operations be per-

formed as read modify write, especially when modifying individual

inadvertently changed.

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