ADIN1100CCPZ-R7 datasheet(11/80 Pages) AD

11 / 80 page

Data Sheet

ADIN1100

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. B | 11 of 80

Table 8. Pin Function Descriptions (Continued)

Pin No.

Mnemonic1

PU/PD2

Description

CEXT_2

N/A

External Decoupling for LDO Circuit. Connect a 0.1 μF capacitor to ground as close

as possible to this pin. Do not use this pin as a voltage source for an external

circuit.

CEXT_3

N/A

External Decoupling for LDO Circuit. Connect a 1 μF capacitor to ground as close

as possible to this pin. Do not use this pin as a voltage source for an external

circuit.

Power and Ground Pins

16, 17

AVDD_H

N/A

Analog Supply Voltage for the Various Analog Circuits in the Device. This supply

rail can be supplied by 1.8 V to 3.3 V depending on the transmit level configuration.

If AVDD_H is 3.3 V, both 1.0 V p-p and 2.4 V p-p transmit operating modes are

supported. If AVDD_H is 1.8 V, only 1.0 V p-p transmit operating mode is supported.

Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to this pin.

AVDD_L

N/A

Analog Supply Voltage for the Internal LDO Circuits. This supply rail can be

supplied by 1.8 V to 3.3 V. AVDD_L can be connected directly to the AVDD_H

rail in long reach applications or alternatively to the VDDIO rail when the device

is configured with dual supplies for lower power consumption. Connect 0.1 μF and

0.01 μF capacitors to GND as close as possible to this pin.

DLDO_1P1

N/A

Output from an Internal 1.1 V LDO Circuit. This pin can be connected to DVDD_1P1

to eliminate an additional power supply rail. Connect a 0.68 μF capacitor to ground

as close as possible to this pin.

DVDD_1P1

N/A

Input for 1.1 V DVDD_1P1 Supply Rail. When using the internal LDO regulator,

connect this pin directly to the DLDO_1P1 pin. Alternatively, an external 1.1 V rail

can be provided to the DVDD_1P1 pin for greater power efficiency. Connect a 0.1

µF to ground as close as possible to this pin.

VDDIO

N/A

3.3 V, 2.5 V, or 1.8 V Digital Power for MDIO and MAC Interface. Connect 0.1 μF

and 0.01 μF capacitors to GND as close as possible to the pin.

EP (GND)

N/A

Exposed Pad (Ground). This GND paddle must be connected to ground. The

LFCSP package has an exposed pad that needs to be connected to GND for

electrical reasons and must be soldered to a metal plate on the PCB for mechanical

reasons. A 4 × 4 array of thermal vias beneath the exposed GND pad is also

recommended.

Other Pins

10, 11, 18, 21

DNC

N/A

Do Not Connect. These pins must be left open circuit.

1 Where a pin is shared between a functional signal and a hardware configuration pin signal, the hardware configuration pin signal is listed last.

2 PU is pull-up, and PD is pull-down. The internal pull-up or pull-down resistor is predefined and non-configurable. N/A means not applicable.

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