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ADIN1100CCPZ-R7 数据表(PDF) 64 Page - Analog Devices |
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ADIN1100CCPZ-R7 数据表(HTML) 64 Page - Analog Devices |
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64 / 80 page  Data Sheet ADIN1100 REGISTER SUMMARY analog.com Rev. B | 64 of 80 PHY Subsystem Reset Register Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST Table 97. Bit Descriptions for CRSM_PHY_SUBSYS_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_PHY_SUBSYS_RST PHY Subsystem Reset. The PHY subsystem reset register allows a managed subsystem reset to be initiated. When the PHY subsystem is reset, normal operation resumes, and the bit self clears. 0x0 R/W SC PHY MAC Interface Reset Register Device Address: 0x1E; Register Address: 0x8815, Reset: 0x0000, Name: CRSM_MAC_IF_RST Table 98. Bit Descriptions for CRSM_MAC_IF_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_MAC_IF_RST PHY MAC Interface Reset. The PHY MAC interface reset register allows a managed PHY MAC interface reset to be initiated. When the PHY MAC interface is reset, normal operation resumes, and the bit self clears. 0x0 R/W SC System Status Register Device Address: 0x1E; Register Address: 0x8818, Reset: 0x0000, Name: CRSM_STAT Table 99. Bit Descriptions for CRSM_STAT Bits Bit Name Description Reset Access [15:2] RESERVED Reserved. 0x0 R 1 CRSM_SFT_PD_RDY Software Power-Down Status. This bit indicates that the system is in the software power-down state. 0x0 R 0 CRSM_SYS_RDY System Ready. This bit indicates that the start-up sequence is complete and the system is ready for normal operation. 0x0 R CRSM Power Management Control Register Device Address: 0x1E; Register Address: 0x8819, Reset: 0x0000, Name: CRSM_PMG_CNTRL Table 100. Bit Descriptions for CRSM_PMG_CNTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_FRC_OSC_EN Force Digital Boot Oscillator Clock Enable. 0x0 R/W MAC Interface Configuration Register Device Address: 0x1E; Register Address: 0x882B, Reset: 0x0000, Name: CRSM_MAC_IF_CFG Configure the MAC interface only by pins. Do not change by software. Table 101. Bit Descriptions for CRSM_MAC_IF_CFG Bits Bit Name Description Reset Access 15 CRSM_RMII_CLK50 This Bit Indicates If the RMII REF_CLK Frequency is 50 MHz or 25 MHz. Only for debugging purposes. Pin dependent R/W 14 CRSM_RMII_CLK_EN CRSM RMII Clock Enable Status. This bit indicates if the RMII clock generation is enabled. Pin dependent R/W |
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