ADIN1100CCPZ-R7 datasheet(37/80 Pages) AD

37 / 80 page

Data Sheet

ADIN1100

APPLICATIONS INFORMATION

analog.com

Rev. B | 37 of 80

For best performance, set the ADIN1100 VCLK_IN signal to 1.0 V

p-p.

Figure 25. External 50 MHz Clock Input Circuit for RMII Mode

For 0.8 V ≤ VS p-p ≤ 1 V (dc coupling), the following results:

►

C1 = 50 Ω (replace capacitor with resistor)

►

C2 not required

For VS p-p > 1.0 V (ac coupling) and C1 and C2 placed near the

ADIN1100 XTAL_I/CLK_IN pin, the following results:

►

C1 = 70 pF maximum

►

C2 = 10 pF

►

CPIN = 3 pF (ADIN1100 pin capacitance)

►

CSTRAY2 ≈ 0 pF

►

VS p-p – VCLK_IN p-p > 0.2 V

►

C1 = VCLK_IN×C2+CSTRAY2+CPIN

Vs−VCLK_IN

Table 28. C1 and C2 Values for Different VS p-p Values with VCLK_IN = 1 V p-p

VS V p-p

C2 (pF)

1.0

Not applicable

50 Ω

1.2

68 pF

1.8

18 pF

2.2

12 pF

2.5

10 pF

2.8

8.2 pF

3.0

8.2 pF

3.3

8.2 pF

The capacitor tolerance from the manufacturer must be included in

the calculations to provide a reasonable margin with regard to the

VCLK_IN target voltage.

Note that additional filtering can be required for the external MAC

module. The selected clock source must be able to supply the

current required by the circuit.

PCB Parasitic Capacitance Considerations

The parasitic capacitance of the clock traces can have a nonnegligi-

ble impact on the signal. The PCB stack and the trace impedance

must be selected carefully to reduce parasitic impedance and pro-

vide the best timing performance, especially if the RMII is selected

(50 MHz clock).

Considering the ac coupling RMII scenario described in the Exter-

nal 50 MHz Clock Input for RMII Mode section, Table 29 displays

some basic calculations of the PCB parasitic capacitance using the

following PCB parameters:

►

Transmit line type: Microstrip Layer 1 and Layer 2

►

Clock trace width: W = 127 μm (5 mils)

►

PCB L1 copper foil thickness after plating: T = 35 μm (1.38 mils)

►

L1 to L2 ground plane distance: H = 0.116 mm (4.55 mils)

►

Substrate relative permittivity: εr = 4.6 (FR4)

In addition, see the IPC-2141 standard for models and guidelines.

Table 29. Trace Parasitic Capacitance Examples

Total Clock Trace Length (cm)

Clock Trace Stray Capacitance (pF)

ELECTROMAGNETIC COMPATIBILITY (EMC)

AND ELECTROMAGNETIC IMMUNITY (EMI)

The ADIN1100 was tested at the system level for EMC and EMI.

Table 30 summarizes the results.

Table 30. EMC/EMI Tests Conducted on ADIN1100 at System Level

EMC/EMI Test

Withstand Threshold/Class

IEC 61000-4-4 EFT

±4 kV

IEC 61000-4-2 ESD (contact discharge) ±4 kV

IEC 61000-4-2 ESD (air discharge)

±8 kV

IEC 61000-4-5 Surge

±4 kV

IEC 61000-4-6 Conducted Immunity

10 V/m

IEC 61000-4-3 Radiated Immunity

Class A

EN 55032 Radiated Emissions

Class B

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