ADIN1100CCPZ-R7 datasheet(4/80 Pages) AD

4 / 80 page

Data Sheet

ADIN1100

SPECIFICATIONS

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Rev. B | 4 of 80

AVDD_H = AVDD_L = VDDIO = 3.3 V; DVDD_1P1 from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1); all specifications at

−40°C to +105°C, unless otherwise noted.

Table 1. General Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUTS/OUTPUTS

Applies to MAC interface pins, MDC,

MDIO, INT, LINK_ST/PHYAD_2, RESET,

and LED_x

VDDIO = 3.3 V

Input Low Voltage (VIL)

0.8

Input High Voltage (VIH)

2.0

Output Low Voltage (VOL)

0.4

Output low current (IOL) (minimum) = 2 mA

Output High Voltage (VOH)

2.4

Output high current (IOH) (minimum) = 2 mA

VDDIO = 2.5 V

VIL

0.7

VIH

1.7

VOL

0.4

IOL (minimum) = 2 mA

VOH

2.0

IOH (minimum) = 2 mA

VDDIO = 1.8 V

VIL

0.3 × VDDIO

VIH

0.7 × VDDIO

VOL

0.2 × VDDIO

IOL (minimum) = 2 mA

VOH

0.8 × VDDIO

IOH (minimum) = 2 mA

RESET Deglitch Time

0.3

0.5

µs

LED/LINK STATUS OUTPUT

Output Drive Current

VDDIO = 3.3 V

VDDIO = 2.5 V

VDDIO = 1.8 V

CLOCKS

External Crystal (XTAL)

Requirements for external crystal used on

XTAL_I/CLK_IN pin and XTAL_O pin

Crystal Frequency

MHz

Crystal Frequency Tolerance

−30

+30

ppm

Crystal Drive Level

<200

µW

Crystal ESR

XTAL_I, XTAL_O Input Capacitance

(CIN,EQ)

1.5

Equivalent parallel differential input

capacitance looking into XTAL_I/CLK_IN

and XTAL_O pins

Crystal Load Capacitance (CL)1

Including PCB trace capacitance and

XTAL_I, XTAL_O CIN,EQ

Start-Up Time

Crystal oscillator only

Clock Input (CLK_IN)

Clock Input Frequency

MHz

Requirements for external clock applied

to XTAL_I/CLK_IN pin, media independent

interface (MII) mode

MHz

Reduced media independent interface

(RMII) mode

Clock Input Voltage Range

0.8

2.5

V p-p

Clock Input Duty Cycle

XTAL_I Input Impedance (ZIN,EQ)

Driving Point Resistance (RP)2

kΩ

RP||CP

Driving Point Capacitance (CP)2

Jitter Tolerance (RMS)

ADIN1100CCPZ-R7 数据表(PDF) 4 Page - Analog Devices

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