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ADIN1100CCPZ-R7 数据表(PDF) 46 Page - Analog Devices |
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ADIN1100CCPZ-R7 数据表(HTML) 46 Page - Analog Devices |
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46 / 80 page  Data Sheet ADIN1100 REGISTER SUMMARY analog.com Rev. B | 46 of 80 Table 44. Ethernet Clause 45 Register Summary (Continued) Device Address Register Address Name Description Reset Access 0x1F 0x800F FC_USZ_CNT Frame Checker Undersized Frame Count Register. 0x0000 R 0x1F 0x8010 FC_ODD_CNT Frame Checker Odd Nibble Frame Count Register. 0x0000 R 0x1F 0x8011 FC_ODD_PRE_CNT Frame Checker Odd Preamble Packet Count Register. 0x0000 R 0x1F 0x8013 FC_FALSE_CARRIER_CNT Frame Checker False Carrier Count Register. 0x0000 R 0x1F 0x8020 FG_EN Frame Generator Enable Register. 0x0000 R/W 0x1F 0x8021 FG_CNTRL_RSTRT Frame Generator Control/Restart Register. 0x0001 R/W 0x1F 0x8022 FG_CONT_MODE_EN Frame Generator Continuous Mode Enable Register. 0x0000 R/W 0x1F 0x8023 FG_IRQ_EN Frame Generator Interrupt Enable Register. 0x0000 R/W 0x1F 0x8025 FG_FRM_LEN Frame Generator Frame Length Register. 0x006B R/W 0x1F 0x8026 FG_IFG_LEN Frame Generator Interframe Gap Length Register. 0x000C R/W 0x1F 0x8027 FG_NFRM_H Frame Generator Number of Frames High Register. 0x0000 R/W 0x1F 0x8028 FG_NFRM_L Frame Generator Number of Frames Low Register. 0x0100 R/W 0x1F 0x8029 FG_DONE Frame Generator Done Register. 0x0000 R 0x1F 0x8050 RMII_CFG RMII Configuration Register. 0x0006 R/W 0x1F 0x8055 MAC_IF_LOOPBACK MAC Interface Loopbacks Configuration Register. 0x000A R/W 0x1F 0x805A MAC_IF_SOP_CNTRL MAC Start of Packet (SOP) Generation Control Register. 0x001B R/W PMA/PMD Control 1 Register Device Address: 0x01; Register Address: 0x0000, Reset: 0x0000, Name: PMA_PMD_CNTRL1 This address corresponds to PMA/PMD Control Register 1 specified in Clause 45.2.1.1 of Standard 802.3. Note that the reset value of this register is dependent on the hardware configuration pin settings. Table 45. Bit Descriptions for PMA_PMD_CNTRL1 Bits Bit Name Description Reset Access 15 PMA_SFT_RST PMA Software Reset. The PMA software reset bit allows the chip to be reset. When this bit is set, the chip fully initializes, almost equivalent to a hardware reset. This bit is self clearing and returns a value of 1 when a reset is in progress. Otherwise, it returns a value of 0. 0x0 R/W SC [14:12] RESERVED Reserved. 0x0 R 11 PMA_SFT_PD PMA Software Power-Down. The PMA software power-down bit puts the chip in a lower power mode. In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still possible. The default value for this bit is configurable via the RX_DV/RX_CTL/SWPD_EN pin, which allows the chip to be held in power-down mode until an appropriate software initialization is performed. 0x0 R/W [10:1] RESERVED Reserved. 0x0 R 0 LB_PMA_LOC_EN Enables PMA Local Loopback. When this bit is set to 1, the PMA accepts data on the transmit path and returns it on the receive path. When this bit is set to 0, the PMA works in normal mode. 0x0 R/W PMA/PMD Status 1 Register Device Address: 0x01; Register Address: 0x0001, Reset: 0x0002, Name: PMA_PMD_STAT1 This address corresponds to PMA/PMD Status Register 1 specified in Clause 45.2.1.2 of Standard 802.3. |
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