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ADIN1100CCPZ-R7 数据表(PDF) 71 Page - Analog Devices |
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ADIN1100CCPZ-R7 数据表(HTML) 71 Page - Analog Devices |
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71 / 80 page  Data Sheet ADIN1100 REGISTER SUMMARY analog.com Rev. B | 71 of 80 Table 112. Bit Descriptions for MMD2_DEV_ID2 Bits Bit Name Description Reset Access [15:10] MMD2_DEV_ID2_OUI OUI Bits. 0x2F R [9:4] MMD2_MODEL_NUM Model Number. 0x8 R [3:0] MMD2_REV_NUM Revision Number. 0x1 R Vendor Specific 2 MMDs in Package Register Device Address: 0x1F; Register Address: 0x0005, Reset: 0x008B, Name: MMD2_DEVS_IN_PKG1 Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. Table 113. Bit Descriptions for MMD2_DEVS_IN_PKG1 Bits Bit Name Description Reset Access [15:0] MMD2_DEVS_IN_PKG1 Vendor Specific 2 MMDs in Package 1. Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present. 0x8B R Device Address: 0x1F; Register Address: 0x0006, Reset: 0xC000, Name: MMD2_DEVS_IN_PKG2 Vendor Specific 1 and Vendor Specific 2 MMDs are present. Table 114. Bit Descriptions for MMD2_DEVS_IN_PKG2 Bits Bit Name Description Reset Access [15:0] MMD2_DEVS_IN_PKG2 Vendor Specific 2 MMDs in Package 2. Vendor Specific 1 and Vendor Specific 2 MMDs are present. 0xC000 R Vendor Specific MMD 2 Status Register Device Address: 0x1F; Register Address: 0x0008, Reset: 0x8000, Name: MMD2_STATUS This address corresponds to the Vendor Specific MMD 2 status register. Table 115. Bit Descriptions for MMD2_STATUS Bits Bit Name Description Reset Access [15:14] MMD2_STATUS Vendor Specific MMD 2 Status. 0x2 R 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address. [13:0] RESERVED Reserved. 0x0 R PHY Subsystem Interrupt Status Register Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system. Table 116. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R LH 14 MAC_IF_FC_FG_IRQ_LH MAC Interface Frame Checker/Generator Interrupt. 0x0 R LH 13 MAC_IF_EBUF_ERR_IRQ_LH MAC Interface Buffers Overflow/Underflow Interrupt. 0x0 R LH |
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