M68HC08 datasheet(21/288 Pages) FREESCALE

21 / 288 page

List of Figures

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

List of Figures

Figure

Title

Page

13-3

USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 169

13-4

USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 171

13-5

USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 172

13-6

USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 174

13-7

USB Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13-8

USB Endpoint 0 Data Registers 0 to 7 (UD0R0–UD0R7) . . . 177

13-9

USB Endpoint 1 Data Registers 0 to 7 (UD1R0–UD1R7) . . . 177

14-1

Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 182

14-2

Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 183

14-3

Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 184

14-4

Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 186

14-5

Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 188

14-6

Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 189

14-7

Data Transfer Sequences for Master/Slave

Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 191

15-1

DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . . . . 196

15-2

DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . . . . 197

15-3

DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . 198

15-4

DDC Master Control Register (DMCR). . . . . . . . . . . . . . . . . . 199

15-5

DDC Status Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 202

15-6

DDC Data Transmit Register (DDTR). . . . . . . . . . . . . . . . . . . 204

15-7

DDC Data Receive Register (DDRR) . . . . . . . . . . . . . . . . . . . 205

15-8

Data Transfer Sequences for Master/Slave

Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 207

16-1

Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 213

16-2

Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 216

16-3

Sync Processor Control & Status Register (SPCSR) . . . . . . . 217

16-4

Sync Processor Input/Output Control Register (SPIOCR) . . . 219

16-5

Vertical Frequency High Register . . . . . . . . . . . . . . . . . . . . . . 221

16-6

Vertical Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . 221

16-7

Hsync Frequency High Register . . . . . . . . . . . . . . . . . . . . . . . 223

16-8

Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . . 223

16-9

Sync Processor Control Register 1 (SPCR1) . . . . . . . . . . . . . 225

16-10 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 226

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