M68HC08 datasheet(65/288 Pages) FREESCALE

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Configuration Register (CONFIG)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Configuration Register (CONFIG)

5.3.2 Configuration Register 1

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32

OSCXCLK cycles instead of a 4096-OSCXCLK cycle delay.

1 = Stop mode recovery after 32 OSCXCLK cycles

0 = Stop mode recovery after 4096 OSCXCLKC cycles

NOTE:

Exiting stop mode by pulling reset will result in the long stop recovery.

If using an external crystal oscillator, do not set the SSREC bit.

COPRS — COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. (See

Section 19. Computer Operating Properly (COP).)

1 = COP timeout period = 213 – 24 CGMXCLK cycles

0 = COP timeout period = 218 – 24 CGMXCLK cycles

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. (See Section 19. Computer

Operating Properly (COP).)

1 = COP module disabled

0 = COP module enabled

Address:

$001F

Bit 7

543

Bit 0

Read:

SSREC

COPRS

STOP

COPD

Write:

Reset:

000

= Unimplemented

Figure 5-2. Configuration Register 1 (CONFIG1)

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