M68HC08 datasheet(92/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

System Integration Module (SIM)

Freescale Semiconductor

In wait mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the wait mode subsection of

each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

7.4 Reset and System Initialization

The MCU has the following reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Illegal opcode

•

Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes

all registers to be returned to their default values and all modules to be

returned to their reset states.

An internal reset clears the SIM counter (see 7.5 SIM Counter), but an

external reset does not. Each of the resets sets a corresponding bit in

the SIM reset status register (SRSR) (see 7.8 SIM Registers).

7.4.1 External Pin Reset

Pulling the asynchronous RST pin low halts all processing. The PIN bit

of the SIM reset status register (SRSR) is set as long as RST is held low

for a minimum of 67 OSCXCLK cycles, assuming that the POR was the

source of the reset (see Table 7-3. PIN Bit Set Timing). Figure 7-3

shows the relative timing.

Table 7-3. PIN Bit Set Timing

Reset Type

Number of Cycles Required to Set PIN

POR

4163 (4096 + 64 + 3)

All others

67 (64 + 3)

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