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M68HC08 数据表(PDF) 90 Page - Freescale Semiconductor, Inc |
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M68HC08 数据表(HTML) 90 Page - Freescale Semiconductor, Inc |
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90 / 288 page ![]() System Integration Module (SIM) Data Sheet MC68HC908BD48 — Rev. 2.1 90 System Integration Module (SIM) Freescale Semiconductor Table 7-2 shows the internal signal names used in this section. Table 7-1. SIM I/O Register Summary Addr. Register Name Bit 7 654321 Bit 0 $FE00 SIM Break Status Register (SBSR) Read: RRRRRR SBSW R Write: Note Reset: 00000000 $FE01 SIM Reset Status Register (SRSR) Read: POR PIN COP ILOP ILAD 0 0 0 Write: POR: 10000000 $FE03 SIM Break Flag Control Register (SBFCR) Read: BCFE RRRRRRR Write: Reset: 0 $FE04 Interrupt Status Register 1 (INT1) Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: RRRRRRRR Reset: 00000000 $FE05 Interrupt Status Register 2 (INT2) Read: 0000 IF10 IF9 IF8 IF7 Write: RRRRRRRR Reset: 00000000 Note: Writing a logic 0 clears SBSW. = Unimplemented R = Reserved Table 7-2. Signal Name Conventions Signal Name Description OSCXCLK Buffered version of OSC1 from the oscillator OSCOUT The OSCXCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = OSCXCLK divided by four) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal |
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