M68HC08 datasheet(64/288 Pages) FREESCALE

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Configuration Register (CONFIG)

Data Sheet

MC68HC908BD48 — Rev. 2.1

Configuration Register (CONFIG)

Freescale Semiconductor

registers are located at $001D and $001F. The configuration register

may be read at anytime.

5.3.1 Configuration Register 0

HSYNCOE — VSYNCO Enable

This bit is set to configure the PTE1/HSYNCO pin for HSYNCO output

function. Reset clears this bit.

1 = PTE1/HSYNCO pin configured as HSYNCO pin

0 = PTE1/HSYNCO pin configured as standard I/O pin

VSYNCOE — VSYNCO Enable

This bit is set to configure the PTE2/VSYNCO pin for VSYNCO output

function. Reset clears this bit.

1 = PTE2/VSYNCO pin configured as VSYNCO pin

0 = PTE2/VSYNCO pin configured as standard I/O pin

SOGE — SOG Enable

This bit is set to configure the PTE0/SOG/TCH0 pin for SOG output

function. Reset clears this bit.

1 = PTE0/SOG/TCH0 pin configured as SOG pin

0 = PTE0/SOG/TCH0 pin configured as standard I/O or TCH0 pin.

TCH0 function is configured by ELS0B and ELS0A bits in

TSC0 (bits 3 and 2 in $0010). (See 10.10.4 TIM Channel

Status and Control Registers (TSC0:TSC1).)

Address:

$001D

Bit 7

543

Bit 0

Read:

HSYNCOE VSYNCOE

SOGE

Write:

Reset:

000

= Unimplemented

Figure 5-1. Configuration Register 0 (CONFIG0)

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