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M68HC08 数据表(PDF) 93 Page - Freescale Semiconductor, Inc |
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M68HC08 数据表(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 288 page  System Integration Module (SIM) MC68HC908BD48 — Rev. 2.1 Data Sheet Freescale Semiconductor System Integration Module (SIM) 93 Figure 7-3. External Reset Timing 7.4.2 Active Resets from Internal Sources SIM module in HC08 has the capability to drive the RST pin low when internal reset events occur. All internal reset sources actively pull the RST pin low for 32 OSCXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 7- 4. Internal Reset Timing). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, or POR (see Figure 7-5. Sources of Internal Reset). Note that for POR resets, the SIM cycles through 4096 OSCXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-4. Figure 7-4. Internal Reset Timing The COP reset is asynchronous to the bus clock. RST IAB PC VECT H VECT L OSCOUT IRST RST RST PULLED LOW BY MCU IAB 32 CYCLES 32 CYCLES VECTOR HIGH OSCXCLK |
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