M68HC08 datasheet(73/288 Pages) FREESCALE

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Central Processor Unit (CPU)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Central Processor Unit (CPU)

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are

disabled. CPU interrupts are enabled when the interrupt mask is

cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but

before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE:

To maintain M6805 Family compatibility, the upper byte of the index

modifies H, then the user must stack and unstack H using the PSHH and

PULH instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return-from-interrupt (RTI) instruction pulls the CPU registers from

the stack and restores the interrupt mask from the stack. After any

reset, the interrupt mask is set and can be cleared only by the clear

interrupt mask software instruction (CLI).

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic

operation, or data manipulation produces a negative result, setting bit

7 of the result.

1 = Negative result

0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic

operation, or data manipulation produces a result of $00.

1 = Zero result

0 = Non-zero result

M68HC08 数据表(PDF) 73 Page - Freescale Semiconductor, Inc