M68HC08 datasheet(96/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

System Integration Module (SIM)

Freescale Semiconductor

7.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An

illegal instruction sets the ILOP bit in the SIM reset status register

(SRSR) and causes a reset.

If the stop enable bit, STOP, in the configure register 1 (CONFIG1) is

logic zero, the SIM treats the STOP instruction as an illegal opcode and

causes an illegal opcode reset. The SIM actively pulls down the RST pin

for all internal reset sources.

7.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal

address reset. The SIM verifies that the CPU is fetching an opcode prior

to asserting the ILAD bit in the SIM reset status register (SRSR) and

resetting the MCU. A data fetch from an unmapped address does not

generate a reset. The SIM actively pulls down the RST pin for all internal

reset sources.

7.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in

stop mode recovery to allow the oscillator time to stabilize before

enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly module (COP). The SIM

counter overflow supplies the clock for the COP module. The SIM

counter is 12 bits long and is clocked by the falling edge of OSCXCLK.

7.5.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU.

At power-on, the POR circuit asserts the signal PORRST. Once the SIM

is initialized, it enables the oscillator to drive the bus clock state machine.

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