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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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M68HC08 数据表(PDF) 48 Page - Freescale Semiconductor, Inc |
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M68HC08 数据表(HTML) 48 Page - Freescale Semiconductor, Inc |
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48 / 288 page  Memory Map Data Sheet MC68HC908BD48 — Rev. 2.1 48 Memory Map Freescale Semiconductor $005A Unimplemented Read: Write: Reset: $005B Unimplemented Read: Write: Reset: $005C Unimplemented Read: Write: Reset: $005D ADC Status and Control Register (ADSCR) Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write: Reset: 00011111 $005E ADC Data Register (ADR) Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: Unaffected after Reset $005F ADC Input Clock Register (ADICLK) Read: ADIV2 ADIV1 ADIV0 00000 Write: Reset: 00000000 $FE00 SIM Break Status Register (SBSR) Read: RRRRRR SBSW R Write: Note Reset: 00000000 Note: Writing a logic 0 clears SBSW. $FE01 SIM Reset Status Register (SRSR) Read: POR PIN COP ILOP ILAD 0 0 0 Write: POR: 10000000 $FE02 Reserved Read: RRRRRRRR Write: Reset: 00000000 Addr. Register Name Bit 7 654321 Bit 0 = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12) |
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