M68HC08 datasheet(95/288 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

System Integration Module (SIM)

Figure 7-6. POR Recovery

7.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of

the COP counter causes an internal reset and sets the COP bit in the

SIM reset status register (SRSR). The SIM actively pulls down the RST

pin for all internal reset sources.

To prevent a COP module timeout, write any value to location $FFFF.

Writing to location $FFFF clears the COP counter and bits 12 through 5

of the SIM counter. The SIM counter output, which occurs at least every

212 – 24 OSCXCLK cycles, drives the COP counter. The COP should be

serviced as soon as possible out of reset to guarantee the maximum

amount of time before the first timeout.

The COP module is disabled if the RST pin or the IRQ is held at VTST

while the MCU is in monitor mode. The COP module can be disabled

only through combinational logic conditioned with the high voltage signal

on the RST pin or the IRQ pin. This prevents the COP from becoming

disabled as a result of external noise. During a break state, VTST on the

RST pin disables the COP module.

PORRST

OSC1

OSCXCLK

OSCOUT

RST

IAB

4096

CYCLES

$FFFE

$FFFF

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