PCA9641PW datasheet(18/55 Pages) NXP

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PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

18 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

8.4 Register 3: Reserve Time register ([B2:B0] = 011b)

Reserve time is for when a master wants ownership of the downstream bus without

interruption. It can reserve from 1 ms to 255 ms ownership of the downstream bus without

interruption.

Reserve time cannot be changed after LOCK_GRANT is one.

If a master requests the downstream bus with 00h in Reserve Time register, this master

wants the downstream bus forever or until it gives up the bus by setting LOCK_REQ bit to

zero.

OTHER_LOCK

R only

This is a status read-only register bit. Other master

lock status indicates the ownership between other

master and the downstream bus. If this register bit is

‘1’, the other master has owned the downstream

bus. If this register bit is ‘0’, the other master does

not own the downstream bus.

The other master does not have a lock on the

downstream bus.

The other master has a lock on the downstream bus.

Table 10.

STATUS - Status register (pointer address 02h) bit description …continued

POR = 00h.

Legend: * default value

Bit

Symbol

Access

Value

Description

Table 11.

RT - Reserve Time register (pointer address 03h) bit description

POR = 00h.

Bit

Symbol

Access

Value

Description

7 to 0 RES_TIME[7:0]

R/W

Reserve timer. Changes during

LOCK_GRANT = 1 will have no effect.

Disable timer or reserve without time limited.

01h

1 ms

FFh

255 ms

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