PCA9641PW datasheet(6/55 Pages) NXP

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PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

6 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

Functional description

Refer to Figure 1 “Block diagram of PCA9641”.

7.1 Device address

Following a START condition, the upstream master that wants to control the I2C-bus or

make a status check must send the address of the slave it is accessing. To conserve

power, no internal pull-up resistors are incorporated on the hardware selectable pins and

they must be connected to VDD, VSS, pull-up to VDD or pull-down to VSS directly. PCA9641

can decode 112 addresses, depending on AD3, AD2, AD1 and AD0, and which are found

in Table 5 “Address maps”.

At power-up or hardware/software reset, the quinary input pads are sampled and set the

slave address of the device internally. To conserve power, once the slave address is

determined, the quinary input pads are turned off and will not be sampled until the next

time the device is power cycled. Table 4 lists the five possible connections for the quinary

input pads along with the external resistor values that must be used.

Table 4.

Quinary input pad connection

Pad connection

(pins AD3, AD2, AD1, AD0)

Mnemonic

External resistor

Min

Max

tie to ground

GND

0 k



17.9 k



resistor pull-down to ground

34.8 k



270 k



resistor pull-up to VDD

31.7 k



340 k



tie to VDD

VDD



22.1 k



Fig 4.

PCA9641 address

R/W

002aab636

programmable

slave address

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