PCA9641PW datasheet(13/55 Pages) NXP

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PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

13 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

8.1 Register 0: ID register ([B2:B0] = 000b)

This register is holding the last 8 bits of the Device ID. It is used to distinguish between

PCA9541 and PCA9641. When a master reads this register, if the value returned from this

8.2 Register 1: Control register ([B2:B0] = 001b)

The Control register described below is identical for both the masters. Nevertheless, there

are physically two internal Control registers, one for each upstream channel. When

master 0 reads/writes in this register, the internal CONTR Register 0 will be accessed.

When master 1 reads/writes in this register, the internal CONTR Register 1 will be

accessed.

Table 7.

ID - Device ID register (pointer address 00h) bit description

POR = 38h.

Address

Bit

Access

Description

00h

7:0

R only

Hard-coded 38h for PCA9641.

Table 8.

CONTR - Control register (pointer address 01h) bit description

POR = 00h.

Legend: * default value

Bit

Symbol

Access

Value

Description

PRIORITY

R/W

Master can set this register bit for setting priority of

the winner when two masters request the

downstream bus at the same time. Table 9 shows

how PCA9641 selects the winner when 2 masters

set their own PRIORITY bit.

Master can configure the priority bit for the case

where two masters request the downstream bus at

the same time. See Table 9 for information on how

PCA9641 selects the winner.

SMBUS_DIS

R/W

When PCA9641 detects an SMBus time-out, if this

bit is set, PCA9641 will disconnect I2C-bus from

master to downstream bus.

Normal operation

Connectivity between master and downstream bus

will be disconnected upon detecting an SMBus

time-out condition.

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