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PCA9641PW 数据表(PDF) 23 Page - NXP Semiconductors |
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PCA9641PW 数据表(HTML) 23 Page - NXP Semiconductors |
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23 / 55 page ![]() PCA9641 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2.1 — 27 October 2015 23 of 55 NXP Semiconductors PCA9641 2-channel I2C-bus master arbiter 9. Arbitration 9.1 Rules 1. If a master keeps its request asserted after its grant, the master will indefinitely hold the bus. – If the bus goes IDLE for 100 ms, it will be disconnected only if the idle time-out function is enabled and the reserve timer has expired. 2. If a master removes its request, then that master will lose its grant. – If the other master is requesting the bus, it will be granted. – If no master is requesting the bus, PCA9641 will disconnect from both. 3. If a master sets the reserve timer before its grant, the timer will clear its request when it expires. – This timer gives a 1 ms to 255 ms window for locking the bus. When the timer expires, it clears the master’s request and follows Step 2. – If the bus is idle for 100 ms and the reserve timer has not expired, the grant will not be lost. – If the master clears its request and the reserve timer has not expired, the grant will be lost. 4. If both masters request the grant at the same time (close), the winner will be determined as follows: – The first master to set the request bit in the register wins. START does not matter, and nothing else really matters as the masters might have different clock frequencies, etc. The master might be doing a burst write with an address rollover, making the control register the last byte it writes. However, if the bit is set in the control register first, it wins. – The action of the grant is applied when the winning master’s transaction is terminated with a STOP. (It is not OK to do a Re-START when requesting the bus; before accessing the downstream slaves, master must issue a STOP.) – If both masters request at the exact same time, and logic cannot determine a winner, the control register priority bit determines which master to give the grant to. See Section 8.2. 5. A write to the control register for a REQUEST will always be answered with an ACK. – The master must poll the control register or use the interrupts to determine when the grant is awarded. 9.2 Disconnect events The following events cause a master to disconnect condition to occur, assuming the conditions from the previous section are satisfied to allow the grant to be removed and the downstream bus to be disconnected. 1. STOP (ideal, this is the cleanest way). 2. Bus IDLE for 100 ms (not ideal). 3. Writing 0 to LOCK_REQ. |
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